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ISO-9001 CERTIFIED BY DSCC
M.S.KENNEDY CORP.
FET INPUT DIFFERENTIAL OPERATIONAL AMPLIFIER
801
(315) 701-6751
4707 Dey Road Liverpool, N.Y. 13088
FEATURES:
10 MHz full power bandwidth min. 650 Volts/s slew rate min. 75 ns settling time to 0.1% max. 100 mA output current min. Replaces H0S-50 Fet Input Available to DSCC SMD 5962-91574
MIL-PRF-38534 QUALIFIED
DESCRIPTION:
The MSK 801 is a high speed, FET input, differential amplifier that exhibits very good DC characteristics. The FET input of the MSK 801 produces low input bias current, input offset voltage and input offset drift specifications. Wide bandwidth, high input impedance, and high output current make it an ideal choice for many high speed/high frequency applications. In addition, the MSK 801 offers the user external compensation, offset null and short circuit protection.
EQUIVALENT SCHEMATIC EQUIVALENT SCHEMATIC TYPICAL APPLICATIONS
TYPICAL APPLICATIONS
D/A Converters Buffer Amplifiers High Speed Integrators Sample and Hold Circuits Video Drivers 1 2 3 4 5 6
1
PIN-OUT INFORMATION
+VCC Output Comp. Comp./Bal. Comp./Bal. Inverting Input Non-Inverting Input 12 11 10 9 8 7 +VC Output -VC -VCC Case NC
Rev. C 8/05
ABSOLUTE MAXIMUM RATINGS

8
See Curve 200mA

ELECTRICAL SPECIFICATIONS
Vcc=15V Unless Otherwise Specified
Group A Parameter Test Conditions 1 Quiescent Current Input Offset Voltage Input Offset Voltage Drift Input Bias Current VIN=0V 2,3 VIN=0V VIN=0V 1 2,3 1 2,3 Input Offset Current Output Current Output Voltage Swing Full Power Bandwidth Bandwidth (Small Signal) Slew Rate Limit (Pulsed) Large Signal Voltage Gain Settling Time to 1% Settling Time to 0.1%
1 12 2
MSK 801B/E Typ. 25 27 0.5 10 50 0.2 10 0.1 Max. 30 32 5 50 500 10 500 5 55 75 75 Min. -
MSK 801 Typ. 25 0.5 10 50 10 Max. 35 10 750 750 65 85 80 Units mA mA mV V/C pA nA pA nA mA V MHz MHz V/S dB nS nS nS dB dB VRMS nV/Hz MHz V/S C/W
Subgroup Min. -
1 2,3 RL=100 VOUT=10V RL=100 f 10MHz RL=100 VO=10V RL=510 RL=100 VO=10V RL=1K VO10V RL=100 VIN=10V RL=100 VIN=10V RL=100 VIN=10V
2 2
4 4 4 4 4 4 4 4 -
100 120 10 10 100 650 50 60 70 200 11.5 12 125 750 70 40 60 200 70 80 1.5 40 250 700 65
100 120 10 11.5 8 90 550 50 55 65 200 12 125 750 70 40 60 200 70 80 1.5 40 250 700 65
Settling Time to 0.01% 1 2 Power Supply Rejection Ratio Common Mode Rejection Ratio Input Noise Voltage
2
VCC=5V VIN=10V f=10Hz to 1KHz f=1KHz
Equivalent Input Noise 2 Gain Bandwidth Product Slew Rate (Sine Wave) Thermal Resistance 2
2 2
RL=510 AV=-20 RL=100 VO=10V Junction to Case @ 125C
NOTES:
1 AV= -1, measured in false summing junction circuit. 2 Guaranteed by design but not tested. Typical parameters are representative of actual device performance 3 4 5 6
but are for reference only. Industrial grade and "E" suffix devices shall be tested to subgroups 1 and 4 unless otherwise specified. Military grade devices ("B" suffix) shall be 100% tested to subgroups 1,2,3 and 4. Subgroups 5 and 6 testing available upon request. Subgroup 1,4 TA=TC=+25C Subgroup 2 TA=TC=+125C Subgroup 3 TA=TC=-55C 7 Consult DSCC SMD 5962-91574 for electrical specifications for devices purchased as such. 8 Continuous operation at or above absolute maximum ratings may adversely effect the device performance and/or life cycle.
2
Rev. C 8/05

VCC Supply Voltage +18V Input Voltage VIN VCC Differential Input Voltage 30V Case Operating Temperature Range TC (MSK 801) -40C to +125C (MSK801B/E) -55C to +125C

TST Storage Temperature Range TLD Lead Temperature Range (10 Seconds Soldering) PD Power Dissipation IOUT Peak Output Current
-65C to +150C 300C
APPLICATION NOTES Heat Sinking
To determine if a heat sink is necessary for your application and if so, what type, refer to the thermal model and governing equation below.
Stability and Layout Considerations
As with all wideband devices, proper decoupling of the power lines is extremely important. The power supplies should be bypassed as near to pins 10 and 12 as possible with a parallel grouping of a 0.01f ceramic disc and a 4.7f tantalum capacitor. Wideband devices are also sensitive to printed circuit board layout. Be sure to keep all runs as short as possible, especially those associated with the summing junction, power lines and compensation pins.
Thermal Model:
Recommended External Component Selection Guide Using External Rf
APPROXIMATE DESIRED GAIN 1 RI(+) 500 1K 820 0 910 0 RI(-) 1K 0 1K 910 1K 1K Rf 1K 0 4.99K 3.6K 10K 9.1K R1 C1
Governing Equation:
TJ=PD x (RJC + RCS + RJC) + TA Where TJ=Junction Temperature PD=Total Power Dissipation RJC=Junction to Case Thermal Resistance RCS=Case to Heat Sink Thermal Resistance RSA=Heat Sink to Ambient Thermal Resistance TC=Case Temperature TA=Ambient Temperature TS=Sink Temperature
1 1
-1 +1 -5 +5 -10 +10
43 0.01f 43 0.01f 120 0.01f 120 0.01f 150 0.01f 150 0.01f
Example:
This example demonstrates a worst case analysis for the op-amp output stage. This occurs when the output voltage is 1/2 the power supply voltage. Under this condition, maximum power transfer occurs and the output is under maximum stress. Conditions: VCC=16VDC VO=8Vp Sine Wave, Freq.=1KHz RL=100 For a worst case analysis we will treat the +8Vp sine wave as an 8VDC output voltage. 1.) Find Driver Power Dissapation PD=(VCC-VO) (VO/RL) =(16V-8V) (8V/100)
=0.64W
1 The positive input resistor is selected to minimize offset currents. The positve input can be grounded without a resistor if desired. 2 This feedback capacitor will help compensate for stray input capacitance. The value of this capacitor can be dependent on individual applications. A 2 to 9 pf capacitor is usually optimum for most applications.
Load Considerations
When determining the load an amplifier will see, the capacative portion must be taken into consideration. For an amplifier that slews at 1000V/S, each pf will require 1 mA of output current. To minimize ringing with highly capacitive loads, reduce the load time constant by adding shunt resistance.
2.) For conservative design, set TJ=+125C 3.) For this example, worst case TA=+50C 4.) RJC=65C/W from MSK 801 Data Sheet 5.) RCS=0.15C/W for most thermal greases 6.) Rearrange governing equation to solve for RSA RSA=((TJ-TA)/PD) - (RJC) - (RCS) =((125C -50C)/0.64W) - 65C/W - 0.15C/W =117.2 - 65.15
=52.0C/W
Case Connection
The MSK 801 has pin 8 internally connected to the case. The case is not electrically connected to the internal circuit. Pin 8 should be tied to a ground plane for shielding. For special applications, consult factory.
3 Rev. C 8/05
APPLICATION NOTES CON'T Slew Rate vs. Slew Rate Limit
SLEW RATE: S=2fVp; Slew rate is based upon the sinusoidal linear response of the amplifier and is calculated from the full power bandwidth frequency. SLEW RATE LIMIT dv/dt; The slew rate limit is based upon the amplifier's response to a step input and is measured between 10% and 90%. MSK measures Tr or Tf, whichever is greater at 10VOUT, RL=100.
Offset Null
Typically the MSK 801 has an input offset voltage of less than 1 mV. If it is desirable to "null" the offset voltage, the circuit below is recommended. RP=10K
Definition of Settling Time
The time required for the output to come within a predetermined error band after application of a full scale step input. This includes the time of delay, slew time and the small signal settling of the amplifier.
Measuring Settling Time
The only accurate method of measuring settling time is by the creation of a false summing junction and observing the error band at that point. The reasons for not using other methods are as follows: Observation of settling at the actual summing junction adds probe capacitance to the input and changes the entire response of the system. (Probe capacitance almost doubles the capacitance at the summing point.) Observing the output is extremely difficult, as the 3% linearity of oscilloscopes, and reading inaccuracies, lead to a possible 5% error. The false summing junction approach works well bcause the amplifier is subtracting the output from the input, and only 1/2 the actual error appears there.
Output Short Circuit Protection
The collectors of the output devices have been brought out to pins 10 and 12 for short circuit protection, if desired. A resistor can be inserted between +VC and +VCC pins, and -VC and -VCC respectively. Resistor values can be selected as follows: RSC (+)VCC = (-)VCC (+)ISC (-)ISC
False Summing Junction Circuit
The addition of the these resistors reduces output voltage swing. Decoupling at VC can help to retain full swing for transient pulses.
Problems: Because the amplifier is to be overdriven, 1/2 the input voltage can be expected to appear at the false summing junction. Therefore, it is necessary to clamp that point with diodes to limit the voltage excursion to avoid overdriving the oscilloscope with the consequent recovery time of the scope itself. The scope probe has capacitance which significantly affects the settling time measurement. Keep the associated resistors as low as possible to minimize the RC time constants, and take into account the added time created by the false summing junction. On the ranges used for settling time measurement even the best real-time scopes suffer from reduced bandwidth and relatively slow settling; a sampling scope is convenient for these measurements.
4
For normal operation and best overall response, short +VCC and +VC and short -VCC and -VC together.
Rev. C 8/05
TYPICAL PERFORMANCE CURVES
5
Rev. C 8/05
MECHANICAL SPECIFICATIONS
NOTE:Standard cover height is 0.200 Max. Alternate lid heights available NOTE: ALL DIMENSIONS ARE 0.010 INCHES UNLESS OTHERWISE LABELED.
ORDERING INFORMATION
Part Number MSK801 MSK801E MSK801B 5962-91574 Screening Level Industrial Extended Reliability MIL-PRF-38534 Class H DSCC-SMD
M.S. Kennedy Corp.
4707 Dey Road, Liverpool, New York 13088 Phone (315) 701-6751 FAX (315) 701-6752 www.mskennedy.com
The information contained herein is believed to be accurate at the time of printing. MSK reserves the right to make changes to its products or specifications without notice, however, and assumes no liability for the use of its products. Please visit our website for the most recent revision of this datasheet.
6
Rev. C 8/05

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